This application claims priority to Korean Application Serial No. 2002-60815, filed Oct. 5, 2002, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having high data bandwidth.
Integrated circuit devices that support high data bandwidth may suffer from simultaneous switching noise (SSN), particularly when switching a plurality of output pins or driving groups of parallel signal lines (e.g., buses) at high frequency. Conventional techniques to reduce SSN have included the use of data inversion circuits that operate to limit the number of parallel data signals that switch value during consecutive data output cycles. For example, FIG. 1 illustrates a conventional data inversion circuit 100 that includes an input XOR circuit 110, a data comparator 130 and an output XOR circuit 120. The input XOR circuit 110 receives a plurality of current input signals FDO1-FDO8 and a plurality of prior output signals DO1-DO8, which are fed back from parallel output pins of the data inversion circuit 100. The XOR logic gates within the input XOR circuit 110 generate a plurality of signals that are provided to inputs of the data comparator 130. This data comparator 130 is configured to generate a single parity signal (S) having a logic value equal to 1 whenever a number of bit differences (xcex94) between the data pairs (FDO1, DO1), (FDO2, DO2), (FD31, DO3), (FDO4, DO4), (FDO5, DO5), (FDO6, DO6), (FDO7, DO7) and (FDO8, DO8) is greater than or equal to four (4). Thus, if the prior value of DO1-DO8=[00000000] and the new value of FDO1-FDO8=[11111110], then the parity signal S will have a value of 1 because A=7. In this case, the new output signals DO1-DO8 will equal [00000001], which means that only one of the output pins will switch value between the old and new output signals. The parity signal S will also be provided as an output of the data inversion circuit 100 so that the circuit or device receiving the output signals can properly interpret their values. In contrast, if the prior value of DO1-DO8=[00001111] and the new value of FDO1-FDO8=[00000001], then the parity signal S will have a value of 0 because xcex94=3. In this case, no data inversion operation will be performed by the output XOR circuit 120 and the new output signals DO1-DO8 will be generated as [00000001].
Another conventional technique for reducing SSN in integrated circuits that output parallel signals to a data bus is disclosed in U.S. Pat. No. 5,931,927 to Takashima. In particular, FIG. 3 of the ""927 patent illustrates an input/output device that generates an m-bit data signal and a single bit parity signal to a bus. Half of the m-bit data signal may be inverted if necessary to make the number of xe2x80x9c1xe2x80x9d signal values more nearly equivalent to the number of xe2x80x9c0xe2x80x9d signal values that are generated during an output cycle. In particular, the ""927 patent shows a Circuit A (left side) and a Circuit A (right side), with each circuit receiving xc2xdm bits of data. If the Circuit A (left side) and the Circuit A (right side) all receive logic 1 signals, then the parity outputs from the two circuits will be equal to xe2x80x9c1xe2x80x9d, which reflects the fact that more xe2x80x9c1sxe2x80x9d than xe2x80x9c0sxe2x80x9d are present. When this occurs, a data inversion flag, which is generated by an exclusive XNOR gate, will be set to a logic 1 value. When the data inversion flag is set to a logic 1 value, then the outputs of the Circuit A (right side) will be inverted by the data inversion circuit. Accordingly, the output buffer (left side) will receive all xe2x80x9c1sxe2x80x9d from the Circuit A (left side) and the output buffer (right side) will receive all xe2x80x9c0sxe2x80x9d from the data inversion circuit. A single-bit output buffer will also generate a flag signal (F1) so that the inversion of the data from the Circuit A (right side) can be properly interpreted once the data is passed to the bus.
Thus, in FIG. 3 of the ""927 patent, if the m-bit data signal provided to circuit A (left side) and circuit A (right side) during a first cycle is: 11111000 and 00000111 and the m-bit data signal provided during a second cycle is: 00000111 and 11111000, then the data inversion flag will not be set and the m-bit data provided to the bus during consecutive cycles will be:                                                                                                                                     1                      st                                        ⁢                                                                  xe2x80x83                                            ⁢                                              xe2x80x83                                                              ⁢                    cycle                    ⁢                                          :                                                                                                                                        xe2x80x83                                                                                                                                          2                      nd                                        ⁢                                          xe2x80x83                                        ⁢                    cycle                    ⁢                                          :                                                                                            ⁢                                                            1                                                  1                                                  1                                                  1                                                  1                                                  0                                                  0                                                  0                                                                              ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                                              0                                                  0                                                  0                                                  0                                                  0                                                  1                                                  1                                                  1                                                                                                        xe2x80x83                        ⁢                                                            0                                                  0                                                  0                                                  0                                                  0                                                  1                                                  1                                                  1                                                                              ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                  ↓                                                                              1                                                  1                                                  1                                                  1                                                  1                                                  0                                                  0                                                  0                                                                          ⁢          xe2x80x83        ⁢    Δ    ⁢      xe2x80x83    =  16
Thus, using the circuit of FIG. 3 of the ""927 patent, the number of xe2x80x9c1sxe2x80x9d and xe2x80x9c0sxe2x80x9d generated during the first cycle are equivalent (at eight each) and the number of xe2x80x9c1sxe2x80x9d and xe2x80x9c0sxe2x80x9d generated during the second cycle are also equivalent (at eight each). However, the number of bit differences (A) from the first cycle to the second cycle will equal a maximum of sixteen (i.e., xcex94=16), which means that all output signal lines to the bus will be switched high-to-low or low-to-high when passing from the first cycle to the second cycle. This high level of switching can lead to unacceptable simultaneous switching noise, even if the total number of xe2x80x9c1sxe2x80x9d and the total number of xe2x80x9c0sxe2x80x9d during the first and second cycles is maintained at about an equivalent level.
Accordingly, notwithstanding these conventional techniques for reducing simultaneous switching noise, there continues to be a need for data inversion circuits that can handle high data bandwidths with high degrees of immunity from SSN.
Integrated circuit devices according to embodiments of the present invention reduce simultaneous switching noise (SSN) when performing high data bandwidth switching operations. These devices also enable the interleaving of data onto data pins in a serial format from data that was originally generated and processed in a parallel format. The parallel format data may be generated within a memory device, such as a dual data rate (DDR) memory device with 4-bit prefetch, or other device that is configured to drive a plurality of signal lines with parallel streams of data, including bus driver circuitry.
In some embodiments of the present invention, a data inversion circuit is provided that processes new data in parallel and also evaluates the new data relative to previously generated output data, which is fed back as an input to the data inversion circuit. In particular, the data inversion circuit is configured to evaluate bit differences between the first and second ordered groups of data received in parallel at inputs thereof by performing bit-to-bit comparisons between corresponding bits in the first and second ordered groups of data. The data inversion circuit is further configured to generate a version of the first ordered group of data in parallel with an inverted version of the second ordered group of data at outputs thereof when a number of bit differences between the version of the first ordered group of data and the second ordered group of data is greater than one-half the number of bits of data within the second ordered group of data. The version of the first ordered group of data may be a noninverted version or an inverted version of the data.
To reduce the delay of a timing critical path associated with the data inversion circuit, a plurality of essentially parallel timing paths are provided in some embodiments of the present invention. In particular, the data inversion circuit may be configured to include a first XOR circuit that is configured to receive the first and second ordered groups of data received in parallel at the inputs of the data inversion circuit. A second XOR circuit is also provided. The second XOR circuit is configured to receive an inverted version of the first ordered group of data and the second ordered group of data. The inverted version of the first ordered group of data may be generated by an inverter circuit.
The data inversion circuit may also include a first comparator that is configured to generate a noninverted parity signal (NPi) in response to signals generated by the first XOR circuit, and a second comparator that is configured to generate an inverted parity signal (IPi) in response to signals generated by the second XOR circuit. A selector circuit may also be provided. The selector circuit is configured to generate a second parity signal (S2) in response to a first parity signal (S1) and the noninverted and inverted parity signals (NPi and IPi). The selector circuit is preferably configured so that the noninverted parity signal (NPi) is selected as the second parity signal when the first parity signal is false (e.g., S1=0) and the inverted parity signal (IPi) is selected as the second parity signal when the first parity signal is true (e.g., S1=1).
Integrated circuit devices according to further embodiments of the present invention include a data inversion circuit that is configured to evaluate at least first and second ordered groups of current input data in parallel with an ordered group of prior output data. In particular, the data inversion circuit includes primarily combinational logic that is configured to output inverted or non-inverted versions of the first and second ordered groups of current input data as first and second ordered groups of current output data, respectively. This primarily combinational logic is configured to maintain a number of bit inversions (xcex94) between the ordered group of prior output data and the first ordered group of current output data at less than or equal to one-half a size of the first ordered group of current output data. The logic is also configured to maintain a number of bit inversions between the first ordered group of current output data and the second ordered group of current output data at less than or equal to one-half a size of the second ordered group of current output data. In this manner, the number of signal lines or pins that undergo switching from one cycle to the next cycle can be kept relatively small to thereby inhibit simultaneous switching noise.